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Latch up of SCR ESD protection device2019/10/02



The process structures of chipset that effect     high speed interface have a huge progress. It would let chips become more sensitive or easy to be damaged by ESD/EOS event. It is a big challenge to provide enough protect ability device for ESD component designer.


When we use ESD protection device which have SCR (Silicon Controller Rectifier) structure, its I-V curve have snap-back characteristic. (Figure 1.) This document will explain the latch up conditions and how to avoid latch up happen at SCR ESD device.


Base on the analysis, Amazing follow the design rule to develop ESD protection device and provide latch−up free devices.

Figure 1. SCR TVS I-V curve


The definition of latch up


The latch up condition would be triggered by transient (just like ESD, surge, or EMI radiation) lead to protection device turn on. The latch up phenomenon is the TVS keeping in on state, even the transient has already decayed. (Figure 2.)


Figure 2. SCR TVS keep in on state


If the power source can provide sufficient voltage (Vbias) and current (Ibias) on the TVS, it can remain the device keep in on state. So latch up need fulfill two conditions : Vbias > Vhold and Ibias > IholdAnd if Vbias < Vhold, or Ibias < Ihold or power off, latch up will be terminated. TVS keep in the latch up would suffer huge current and it will cause TVS damage. Another effect is that the voltage would be holding on a low level by TVS in conduction. It may lead to signal or power rail can’t reach normal voltage level.


How to decrease latch up risk?


Due to CMOS process will keep going on advanced development. The chips itself protection ability will be worse than before, so to improve clamping voltage (Vclamp) play an important role to develop TVS. But if Vhold < Vbias, TVS would under the big risk of latch up.(Figure 3.)


Figure 3. Vhold out of safe operation area


Amazing designer follow Vhold must be over Vbias rule to provide latch up free TVS device.(Figure 4.)


Figure 4. Vhold in safe operation area


The TVS safe operation area is between signal operation area (VDD+10% tolerance) and the chips hardware damage voltage (Vmax).


The real case of latch up


USB Type-C was widely used in electronic product until now. The CC pin of Type-C connector is used as the identification external device. It usually be pull-up to 5.5V (max). Amazing have been set up a test environment to prove SCR TVS


(non-Amazing parts) which Vhold=2.5V < Vbias=VDD=5V (Figure 5.) gonna lead to latch up.


Figure 5. Vhold< Vbias TLP I-V curve.


Amazing set an experiment to duplicate it as below. (Figure 6.)


Figure 6. Use ESD Gun to trigger TVS into latch up at 5V/30mA test condition.


After ESD inject transient event to trigger TVS turn on, we observe pull-up level 5V drop to Vhold=2.3V. (Figure 7.) It will affect signal transmission and cause the TVS to be damaged.



Figure 7. 5V be latch on 2.3V


This case point out Vrwm is a TVS datasheet’s key parameter. For example, some vendor mark TVS Vrwm=5V but Vhold=2.5V. If system engineer use this part at the application circuit which have huge DC current, the TVS will have a big risk to let latch up happen. We can refer to a experiment as below. Amazing set a test for AZ5B75-01B, it Vhold > Vrwm.(Figure 8.)


Figure 8. AZ5B75-01B TLP I-V curve


We also inject ESD event into AZ5B75-01B and observe its response. The test result is on the below table. (Figure 9.)



Figure 9. After ESD event passed, AZ5B75-01B does not occur latch up.


We can find out AZ5B75-01B still keep level at 5V and don’t have any abnormal phenomenon. Amazing guarantee provide latch up free component, make sure Vhold > Vrwm to avoid any latch up possibility. Latch up free TVS can make sure system product without latch up issue. So adopting Amazing TVS is your best choice.



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Amazing Microelectronic Corp. is the first professional ESD/EOS solutions provider in Taiwan. Our vision is to provide the ESD/EOS total solutions for our customers.

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