The Best Solution of ESD/EOS for DP2.0 Application

As the demand for high-definition images gradually increases, display without a high-resolution is impossible to meet the needs of users. VESA released the DP2.0 specification that can provide up to 80Gbps transmission rate. With its excellent transmission performance, it can output images with the best resolution of 16K@60Hz and 8K@120Hz to meet user requirements. In order to realize such a high transmission speed, the DP2.0 control chip must use advanced semiconductor manufacturing technology, but it also causes the DP2.0 control chip's ability to withstand electrostatic discharge (ESD) to rapidly decline.

DP2.0 is divided into three different standards. It is divided into UHBR 10, UHBR 13.5, and UHBR 20 (as shown in Figure 1) by bandwidth. UHBR 10 has a bandwidth of 10Gbps per channel. Both DisplayPort and USB Type C interfaces can be utilized. However, UHBR 13.5 and UHBR 20 are different, which can only be built on the USB Type C interface. This interface can increase the transmission rate to 80Gbps, and the USB PD power supply can reach up to 100W for power delivery.

Figure 1: DisplayPort 2.0: UHBR Modes

In the future, the USB Type C interface will become the mainstream interface for consumer electronic products such as TVs, monitors, personal computers, and laptops. Similar to conventional USB, USB Type C is a plugging interface that is exposed to users at any time in the system. The most common application is plug to play and unplug to turn off. However, this hot-plugging action often causes electronics to work abnormally and even causes the damage of USB Type C control components, because such actions are quite easy to cause transient noise problems such as ESD. In hot plugging, since the signal line at the interface is already charged and this charged cable will form a discharge action when it contacts the system. This phenomenon is equivalent to the electrostatic discharge effect that will cause serious damage to the system. This phenomenon is generally called direct discharge. At present, in the electrostatic discharge test of the system, more and more manufacturers require the direct-pin injection method to test their products so as to simulate the ESD events that the system suffers most frequently when the system is used by users.

With respect to ESD system test requirements, in addition to the IEC61000-4-2 regulation, some brand manufacturers even specify that their USB Type C connectors need to pass the ±8kV ESD bombardment by the Direct-Pin Injection test method. Therefore, it is absolutely necessary to use ESD protection components on the USB Type C interface to prevent ESD events from interfering with data transmission.

For the high-speed interface of DP2.0, when selecting ESD/EOS protection components the following must be considered: 

1.      In order to ensure the signal integrity during DP2.0 high-speed signal transmission, when choosing ESD protection components, choose ESD protection components with a lower parasitic capacitance. It is recommended that the parasitic capacitance be less than 0.2pF 

2.      The protection component must have a high tolerance to ESD, at least to be able to withstand the 8kV ESD bombardment of IEC 61000-4-2 contact mode. 

3.      SD Clamping voltage is the most important reference parameter. For ESD protection components to provide effective protection to the system, it is most important to consider whether the clamping voltage is low enough so that the ESD energy can be clamped to a lower voltage to prevent the internal circuits of the system from being interfered or damaged. This clamping voltage is the most important parameter for determining the effectiveness of ESD protection components for system circuit protection. 

4.      USB PD charging technology can support four voltages (5V/9V/15V/20V). Frequent hot-plugging of power cords will easily cause ESD/EOS problems. Therefore, a more complete external surge ESD/EOS protection solution design must be adopted in the system.     

Amazing Microelectronic Corp. has advanced ESD protection design technology, AZ5B0S-01F is launched especially for the needs of DP2.0. In order to avoid the parasitic capacitance of the protective components from affecting the high-speed transmission of DP2.0 differential signals, the parasitic capacitance of AZ5B0S-01F has been lower than 0.2pF, which can pass the Eye Diagram test easily. The most important thing is that the AZ5B0S-01F has a very low ESD clamping voltage, which can effectively help the DP2.0 interface pass Direct-Pin Injection±8kV electrostatic discharge bombardment. Figure 2 shows the current versus voltage curve of the AZ5B0S-01F measured by TLP. Under IEC 61000-4-2 contact mode 8kV ESD bombardment (equivalent TLP current is about 16A), the clamping voltage is only 5.5V, which can effectively prevent system products from data errors, crashes or even damage during ESD testing.

Figure 2 ESD clamping voltage characteristic curve of AZ5B0S-01F

The remaining signal lines (AUX/D+/D-/CC/HPD) are recommended to use AZ5515-02F in DFN1006P3X package. Its single unit can withstand the energy of IEC61000-4-5 (8/20µS) at about 11A, and the ESD clamping voltage is only 10V@16A (as shown in Figure 3).

Figure 3 ESD clamping voltage characteristic curve of AZ5515-02F

This interface can also provide power delivery. At the power end, a suitable EOS protection component (as shown in the figure AZ3105-01F/AZ4510-01F/AZ4516-01F/AZ4520-01F) should be selected according to the designed voltage for protection so as to completely protect this interface from the threat of ESD/EOS. Figure 4 shows the complete DP2.0 interface ESD/EOS solution protection circuit.

Figure 4 ESD/EOS solution protection circuit of DP2.0 interface