TVS Selection in High Speed Interface with Parasitic Capacitance Consideration

Abstract: 

The selection of TVS is closely related to the application interface that it protects. The operating voltage of TVS must be equal to or greater than that of the protected line, and the parasitic capacitance of TVS must be considered if the TVS is used for high-speed transmission interface protection, or the signal integrity will be compromised, leading to the inability to read signals due to distortion of signal transmission waveforms. On the other hand, some hardware engineers ask for extremely low capacitance TVSs for signal lines as some kind of obsession for signal integrity. The result is often the excessive clamping voltage in the handful of protection devices available for selection, which could seriously downgrade the efficiency of TVS protection and fail the intention of ESD protection design solution. 

This article explains TVS selection from the point of view of high-speed interface transmission. The maximum allowable capacitance for high-speed signals is estimated using return loss, thus keeping engineers from selecting a protection solution with overly small or large capacitance.  

What parasitic capacitance does to distort high-speed signals 

As shown in Figure 1 below, the ground capacitance of a signal line increases the rising and falling time of signal, which leads to signal waveform distortion. The greater the ground capacitance, the slower the signal slew rate, as shown in Eq. 1 and Eq.2 below. When the signal is too distorted for IC to identify, an error code occurs. That is why the bit time must be increased to solve the error codes in case of high parasitic capacitance, so that there is enough time for signals to rise or fall within the thresholds, but the signal transmission will be slower in this case. 

For Rising State:                                   V(t)=V_0 (1-e^(-t/RC))             Eq. 1

For Falling State:                                  V(t)=V_0 (e^(-t/RC))                Eq. 2

Fig. 1 Impact of capacitance on signal distortion

However, it is hard to quantify how much capacitance will lead to error code. For this, the time domain is converted into frequency domain via fast Fourier transformation (FFT) in high-speed digital signal or RF circuit designs; i.e., the S-parameters, such as S11 return loss and S21 insertion loss. 

High-frequency signal attenuation and capacitance considerations

The S11 return loss is the ratio between reflected wave and incident wave as electromagnetic waves reflect between two interfaces when impedance mismatches. In its application in circuits, TVS is connected to ground in parallel with terminal impedance. Thus, the capacitance load increases and the impedance change. 

First of all, let’s assume the single-ended transmission line with characteristic impedance of 50 Ohm. In general, the impedance matching is determined if the S11 is smaller than -10dB or not. When S11 < -10dB, more than 90% of the incident power is transmitted to the loading end. Next, the estimated capacitance is determined at various operating frequencies. The red line in Figure 2 helps us determine the upper limit for TVS parasitic capacitance in different speeds. 

Fig. 2 Allowable capacitance loading under different return losses

Take USB4 as an example: the maximum transmission of a Tx/Rx can be as fast as 20 Gbps, and the operating frequency is equivalent to a fundamental frequency of 10 GHz. Therefore, it is seen in Figure 2 that the maximum allowable parasitic capacitance is 0.29 pF for a high-speed line with S11= -10 dB. In addition, the TVS capacitance is assessed based on S21 insertion loss using the same method. The assessment results are the same using either S11 or S21, since the power of attenuated transmit wave caused by ground capacitance is the insertion loss, S21. However, the tolerance of signal attenuation varies from one transmission interface to the others, and so does the redundancy available for TVS from one system design to the other. At the end, the parasitic capacitance to be tolerated by TVS is verified from the eye diagram test of each interface. 

Amazing Microelectronic’s high-speed interface ESD solutions

Amazing Microelectronic features a wide range of high-speed interface ESD solutions with the highest specifications available in the industry. There are solutions for USB, HDMI, LAN port and more, as listed in Table 1 below. AZ5B9S-01F has a parasitic of merely 0.18pF, and provides a clamping voltage of 4.6V, lowest in the industry, in the same DFN0603 package. This is the best selection for USB4 re-timer/controller that one can find. Amazing Microelectronic has been in this industry for decades and close partnership with major clients helps our products match seamlessly market demands. The signal quality and ESD protection of high-speed interface is ensured while we are working with clients with ESD issues. 

Table 1. ESD solutions provided by Amazing Microelectronic