IP Camera LAN Port ESD/Lightning Protection Solution

The damage to electronic elements and components induced by ESD/lighting needs to be considered at the beginning of electric communication product design. An electrostatic discharge (ESD) / lighting verification is often performed from design to the hand of end users. Lightning can cause serious damage to chips and, thus, major losses to companies. A lot of design attention is focused on protection against lighting and the like.

IP cameras (IPCs) are very common to record real-time images at places like school and banks where the safety of students and teachers or financial records are important. IPC is a new-generation camera that combines traditional camera and network technology. The images are transmitted to remote equipment located off site through Internet, allowing a remote user to view the audio and video feeds in real time by way of online browser without the need for any specialized software program. An authorized user may control the actions and system configuration of the pan/tilt lens of IPC. A poor design of IPC product against ESD or Lightning compromises not only the product acceptability of the equipment production company, but also how end users feel about the product. Issues like this have direct impacts on the images and status of the product in the market. That’s why the protection against ESD and lightning is an indispensable part of electronic product design. 

 1. What hazards can ESD bring

Moore mentioned in an article published in a magazine in 1960s that the number of transistors integrated on a semiconductor will grow exponentially over time; the evolution we have seen in products is the perfect example. For example, computers have evolved from desktop version to laptops, and cumbersome handheld cell phones have evolved into smart phones with 6” display. The difference is not only in size, but also in functionality and product performance. Thanks to advanced lithography machines that push chip manufacturing forward, the manufacturers are allowed to design more transistors on wafers of the same size. The more advanced the IC manufacturing process is, the closer the transistors are to one another, and the vulnerable the chips are to ESD. As a piece of equipment is subject to external ESD pulses, it may produce information reading errors or circuit faults if the pulses find their way into sensitive circuits. 

2. What is lacking in existing ESD protection solutions

There are things that existing ESD protection solutions cannot do. In addition to ESD protection design, Electrical Over-stress, or EOS, requires attention as well. For easy connection, outdoor IPCs are mostly powered via POE, where the network cables and power cables are run through the same cable trough. For an outdoor configuration, equipment is often subject EOS coming from natural lightnings as well as utility power fluctuation. The test standards for ESD and EOS are IEC61000-4-2 and IEC61000-4-5, respectively. Compared to the test waveforms for ESD, EOS test waveforms feature long duration and powerful destruction capability (Fig. 1). With the same voltage conditions, EOS can do greater damage to chips. Furthermore, IPC equipment is mostly located outdoors. That’s why lightning surge test is simulated for IPC design.

  Figure 1. Difference between ESD and EOS

3. ESD and lightning protection at LAN port

LAN is a typical external interface in an IPC product. It is necessary to understand peak pulse current (IPP) as a lightning parameter (tp=8/20ms) when selecting a TVS element. For TVS application on the secondary side of RJ45, Amazing Microelectronic came up with AZ1513-04S. A Line-GND common mode rejection solution, AZ1513-04S features SOT23-6L packaging. It provides protection for 4 IOs and a power supply, as well as low clamping voltage for ESD and EOS (Fig. 3). For Line-Line differential mode rejection solution, the SOT23-6L-packaged AZ1603-02S was launched to match the differential pair impedance in PCB layout with flying colors. During the signal transmission test over 10/100/1000M network, the parasitic capacitance requirement is high also for TVS elements. The extremely low parasitic capacitance parameters of AZ1513-04S and AZ1603-02S, as provided in Table 1, take care of the redundant parasitic capacitance requirement for long-cable communications between various IPC equipment and mainframe.

Figure 3. AZ1513-04S surge and TLP tests

The lightning protection design for LAN port is demanding for PCB layout. It has to meet the spacing requirement between the primary and secondary sides of network transformer and the differential pair impedance requirement. In the PCB layout for TVSs, the signal wiring has to go through TVS first and needs to be as short as possible. This way, the TVS is activated more quickly to release current when an ESD or EOS surge strikes. 

In summary, it is a common practice to add a large-current anti-lightning element on the primary side of network transformer for IPC products. However, there is the issue of excessive clamping voltage, resulting in product damage as some of the energy is transmitted to rear end circuit through the coupling with primary and secondary distribution capacitors. When differential mode voltage is created between differential lines, energy goes to secondary through the coupling with primary coil of network transformer, which leads to PHY chip damage if excessive current is not drained through TVS. Therefore, the protection at the secondary side of network transformer is important. The common test criteria adopted by IPC manufacturers are ±6kV CM for common mode test voltage and ±3.5kV DM for differential mode test voltage. The analogue lightning test satisfies products’ ability against lightning at specific places, reduces product malfunctions caused by environmental factors and, thus, save repair costs and better maintain reputation.

Table 1