Network ports are fairly common on products like NB, MB, IP-CAM and others. It is not uncommon to lay network cables outdoors, which makes network highly vulnerable to EOS surge interference. That is why it is necessary to have efficient ESD/EOS protection strategy for network ports.
A network port consists of 3 parts from the outside in, as shown in Figure 1: (1) RJ45 connector, (2) Transformer, and (3) LAN PHY. From (1) to (2), it is called the primary side. When the surge test conditions are harsh, devices with greater surge tolerance may be considered at the center of transformer on the primary side to protect the Bob Smith circuit. From (2) to (3), it is the secondary side where the protection devices are located, as the latest circuit design trend, to suppress the surge energy after transformer is isolated, which greatly reduces the vulnerability of LAN PHY at the rear end to the threats of external interference. Sometimes, there are protection devices with greater surge energy tolerance at the primary side, such as the SIDACtor. However, the clamping voltage of these devices are so high that the energy still finds its way to couple with the secondary side in surge or ESD test, or even leads to crash or damage in the case of LAN PHY. That is why ESD/EOS protection is suggested at the secondary side to prevent tragedies like these from happening. On the other hand, caution is advised for the parasitic capacitance of the selected ESD/EOS device, since the secondary side protection devices are located on the network signal lines, or the signal quality is vulnerable in this case.
Figure 1 Network port architecture
The surge test is performed on a network port in one of two modes, differential mode and common mode. Therefore, the selection of material varies depending on the protection strategy. For the differential mode, the surge test is performed between differential signal lines, in which case a bidirectional device is recommended. Figure 2 shows how a surge device is connected in the surge test in differential mode.
Figure 2 Protection device connection in the differential mode surge test
When it comes to the common mode, the surge test is conducted on all network signal lines. Most of the energy is dissipated at the primary side, but a small portion of the energy still finds its way to the secondary side, and this is when the secondary-side ESD/EOS production device kicks in to redirect the common mode surge test to ground, as shown in Figure 3.
Figure 3 Protection device connection in the common mode surge test
| Interface | Protection | Parts | Package | VRWM (V) | VBR (V) | Vclamp(ESD) | CIn(Typ.) | Ipp(8/20µs) |
|---|---|---|---|---|---|---|---|---|
| 10/100/1000Mbps Ethernet |
Line to GND | AZ1213-04F |
4 I/O Pins DFN2510P10E 2.5x1.0x0.5 mm |
3.3 | 5 | 6.5 | 2.1pF | 20A |
| Line to Line | AZ3125-08F |
4 I/O Pins DFN3020P10E 3x2x0.55 mm |
2.5 | 3 | 8 | 1.7pF | 45A | |
| LED control signal | AZ5883-01F |
1 I/O Pins DFN1006P2E 1.0x0.6x0.5 mm |
3.3 | 4.5 | 5 | 70pF | 52A | |
| 2.5/5/10Gbps Ethernet |
Line to GND | AZ1123-04F |
4 I/O Pins DFN2510P10E 2.5x1.0x0.5 mm |
3.3 | 5 | 10 | 0.2pF | 6.5A |
| Line to Line | AZ5B0S-01F |
1 I/O Pins DFN0603P2Y 0.6x0.3x0.3 mm |
2 | 5.5 | 5.5 | 0.18pF | 7A | |
| Line to Line | AZ522S-01F |
1 I/O Pins DFN1006P2E 1.0x0.6x0.5 mm |
2 | 5.5 | 6.5 | 0.2pF | 6.5A | |
| LED control signal | AZ5883-01F |
1 I/O Pins DFN1006P2E 1.0x0.6x0.5 mm |
3.3 | 4.5 | 5 | 70pF | 42A |
Table 1 Ethernet ESD/EOS protection solution families
Amazing Microelectronics has several network port ESD/EOS protection solutions listed in Table 1. With the 10Gbps port as an example, two packaging choices are suggested for differential mode protection, the AZ5B0S-01F in DFN0603P2Y(0201) package or AZ522S-01F in DFN1006P2E(0402) package. Both devices have a parasitic capacitance around 0.2pF. A single device can take up to 6.5A or so of IEC61000-4-5 surge (8/20μs). For the common mode protection, the 4-channel AZ1123-04F is recommended with a parasitic capacitance of nearly 0.2pF, and a single device can take approximately 6.5A of IEC61000-4-5 surge (8/20μs). The AZ1123-04F is in DFN2510P10E package, and feed-through is possible for PCB Layout, providing greater flexibility for design, as shown in Figure 4. For the EOS/ESD protection of the 10Gbps port above, the recommended protection devices feature little parasitic capacitance with little impact on signal quality, and a single piece has good tolerance, suitable for locating on high-speed signals at network port.
Figure 4 PCB Layout for 10Gbps network port ESD/EOS devices
In addition, years of experience in network port ESD/EOS tests indicates that the coupling of EOS or ESD (air discharge) energy to RJ45 LED control signals often leads to LAN PHY damage, as shown in Figure 5. It is suggested to add protection to LED control signal lines in circuit design, as to prevent this from happening.
Figure 5 Network port ESD test
Network has become an essential tool of everybody’s daily life. For this, it is recommended to have protection strategy built in circuit in the early stage of system design in order to prevent the problem of failure in safety standard tests while minimizing the issues of network port defects in the market due to EOS/ESD. If it is decided to skip the protection in low-level products due to economic consideration, it is recommended to reserve a package position for protection device in the circuit design, as this helps prevent lots of product repair issues and even the difficulty of time-consuming and labor-intense upgrades as a brand-name customer requests higher specifications.