In this year's hot topic of USB TYPE C, the USB TYPE C port connection application is the most popular new application port. It was released by the USB Implementers Forum (USB-IF) and was completed in August 2014. The biggest feature of the appearance is that the upper and lower signals of the port are completely symmetrical. When connecting, users are not limited by the conventional Micro-USB port application, which needs to distinguish between the front and back sides of the USB. USB TYPE C can be directly inserted by either side.
Existing technology application products focus on high-efficient application outputs with convenience, so the applications can be widely applied to portable devices, VR devices through USB TPYE C. When receiving IEC61000 -4-2 static protection test, the keyboard/button are inevitably subject to the influence of electrostatic energy, causing an abnormal phenomenon in the system, which will eventually cause serious damage to the electronic products. EOS (Electrical Over Stress) refers to all the excessive electrical stress. When the external current or voltage exceeds the maximum specification of the device, device performance may be impaired or even damaged.
At the beginning of product design, the ESD/EOS protection design specifications must be taken into consideration. When selecting TVS protection components, it is necessary to select both ESD/EOS protection components.
For portable devices using USB TYPE C applications, it is often limited by PCB area and it is not easy to select suitable TVS protection components. For this application requirement, AMAZING Microelectronic Corp. has advanced ESD protection design technology to develop package specifications for market-end applications with the Array architecture specification. The printed circuit board (PCB) of the product is getting smaller and smaller under the trend of thinner and lighter electronic products, but the line becomes more complicated under the strong functional requirements of the product. As a result, the area of the PCB has become very crucial and it has caused considerable trouble in product design.
Criteria for the protection component applied to the keyboard/button connection port
The ESD protection component to be used in the keyboard/button signal must meet the following three criteria:
First, the ESD protection component itself must have the Peak Pulse Current parameter for better EOS protection.
Second, the protective components must have high tolerance to ESD and must at least withstand the bombardment of IEC 61000-4-2 contact mode 8kV ESD.
Third, the package size of the ESD protection component design should not be too large (not recommended to be placed over 2.0mm x 2.0mm) to avoid the trouble that ESD protection components cannot be placed on the PCB circuit board of the keyboard/button application.
Fourth, the most important requirement is that the clamping voltage provided by the protective element during the ESD event must be low enough so as not to cause damage to the transmitted data.
The above four criteria are indispensable. Missing any of the key criteria, the button/keyboard signal cannot be fully protected. However, ESD protection components that meet the above four criteria are very difficult to design.
The package structure of the AZ5515-02F series is the pin of the DFN1006P3X that supports two signals. It can protect the two signals of the button at the same time. It can be optimally selected when the PCB area is limited but the ESD/EOS protection specifications are required.
Most importantly, the AZ5515-02F has a low ESD clamping voltage that prevents ESD events from interfering with data transmission, allowing an electronic system with a keyboard/button connection to pass the Class-A IEC 61000-4-2 system level electrostatic discharge protection test. After measuring the AZ5515-02F using the Transmission Line Pulse System (TLP), the ESD clamping voltage characteristics of Figure 1 can be observed. In the IEC 61000-4-2 contact mode 8kV ESD shock (TLP current equivalent is about 16A), the clamping voltage is only 10V, which will effectively avoid data errors, crashes and even damage during system ESD testing.
Figure 1. ESD clamping voltage test curve for AZ5515-02F
At the same time, AZ5515-02F has low capacitance characteristics, which can be applied to USB2.0 high-speed signal transmission lines. Refer to the characteristic curve of parasitic capacitance of AZ5515-02F protection component.