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System-Level ESD Protection for USB 3.0 Interfaces2013/01/11

 

USB 3.0 will become the mainstream soon, because it significantly reduces the time required for data transmission, reduces power consumption, and is backward compatible with USB 2.0. USB 3.0 has transmission speed of up to 5 Gbps, which is 10 times faster than USB 2.0. With ultra high speed transfer rate, the USB 3.0 controller chips should be fabricated in advanced semiconductor processes. In such advanced semiconductor processes, the devices with nanometer scale are susceptible to electrostatic discharge (ESD) damage. Moreover, with the support of hot plug capability, ESD is particular threats to USB port due to the discharge event from a user plugging in a charged cable.
 
Currently, all electronic systems are expected to sustain the ESD level of ±8kV (±15kV) under contact-discharge (air-discharge) test mode to achieve the immunity requirement of “level 4” in the IEC 61000-4-2 test standard. In the traditional system-level ESD test, the ESD stress is only on the casing of systems to verify the ESD robustness. But now, more and more system houses have adopted the direct-pin injection test on the USB ports to simulate the real-world ESD stresses on systems. Some system houses have even defined the ESD test specification that the systems should pass ESD level of ±8kV by direct-pin injection on USB ports.
 
Transient voltage suppressors (TVS) are often added on the system boards to protect the ICs against ESD-induced system malfunction and/or damage to ICs under system-level ESD test. To meet the ESD test specification by direct-pin injection on USB ports, the TVS added on the system boards to protect the USB interfaces are necessary. The TVS specifications for USB 3.0 interfaces should meet the following requirements:
(a) Low ESD Clamping Voltage
To provide effective ESD protection, TVS should not only sustain at least the ESD level of ±8kV (±15kV) under contact-discharge (air-discharge) test mode, but also be turned on with low ESD clamping voltage under ESD events. With a lower ESD clamping voltage, the ESD pulse can be clamped to a lower voltage level to prevent the protected circuits from being reset or even damages under ESD events. Therefore the ESD clamping voltage is the most important factor for evaluating the performance of TVS.
(b) Ultra-Low Capacitance
   USB 3.0 is expected to transmit and receive 5 Gbps data, which needs differential signaling. For differential signaling, it’s important to keep the differential impedance at constant. TVS devices have an inherent junction capacitance. Usually, this added capacitance on an USB 3.0 port will cause the impedance of the differential pair to drop to interfere with the signaling. Therefore, the parasitic capacitance of TVS for an USB 3.0 port should be low enough to minimize the impact on signal integrity. The TVS capacitance for an USB 3.0 port is expected to be as low as 0.3pF.
(c) Single-Chip Solution
 
   Because the electronic products are designed to be much smaller than ever, the printed circuit board (PCB) space for placing the TVS becomes much smaller. In addition, the cost of TVS with multi-chip design on the PCB for an USB 3.0 port will be increased. To save the board space and cost, the TVS array with single-chip design for an USB 3.0 port is the best solution.
 
Amazing Microelectronic Corp. is the leadership in the field of TVS design. AZ1065-series is specifically designed to provide effective ESD protection for an USB 3.0 port. The parasitic capacitance of AZ1065-series is smaller than 0.3pF. With ultra-low capacitance of this TVS, there is nearly no impact in the signal integrity. Most of all, AZ1065-series is designed with ultra-low ESD clamping voltage, which can help the systems pass ESD level of ±8kV by direct-pin injection on an USB 3.0 port. Fig. 1 shows the TLP measured I-V characteristics of AZ1065-series. The clamping voltage is only 13V under 6kV ESD stress (TLP current~17A).
 
In addition, AZ1065-series is a design with single-chip solution for an USB 3.0 port. Fig. 2(a) shows the data lines and power rails connection of AZ1065-series. One AZ1065-series can provide protection for two SuperSpped differential pairs (TX+/TX- and RX+/RX-), USB 2.0 differential pair (D+/D-), and power line (VBUS) of an USB 3.0 port simultaneously. Fig. 2(b) shows the PCB layout of AZ1065-series for an USB 3.0 port. The use of a DFN-10 package with the “feed through” layout can provide a minimum impedance change on the high speed data line. Therefore AZ1065-series is the best ESD solution for an USB 3.0 port.
 
Fig. 1 The TLP measured I-V characteristics of AZ1065 series for USB 3.0 interfaces.
 
(a)
 
(b)
 
Fig. 2(a) The data lines and power rails connection and (b) the PCB layout of AZ1065-series for an USB 3.0 port.
 
 

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