In recent years, with the trend of miniaturization of electronic products, R&D researchers often face the problem of poor PCB GND discharge path due to the small PCB space when designing products, which can easily lead to problems that products cannot pass the ESD/EOS test. In order to successfully passing the IEC-61000-4-2 and IEC-61000-4-5 protection test regulations, it becomes extremely important for R&D to configure protective components on the system circuit. If the placement and routing of the protective components are incorrect, the protective component will not be able to perform its intended effect, and ultimately the main chip will be affected by ESD/EOS, causing system damage or abnormal I/O port functions. This article mainly introduces matters such as the placement of protective components and PCB Layout routings that require special attention when designing protective circuits. It is applicable to various types of protective components in different packages currently on the market.
1. Precautions for the placement of ESD/EOS protection components
Figure 1: Parameters for configuring the placement of protective components during PCB Layout when disassembling them
● As shown in Figure 1, L1 - refers to the distance between the Connector and TVS during PCB Layout. It is recommended that this distance should be shortened as much as possible. At the same time, it is necessary to confirm that the first contact part after the Connector is the TVS protective component. The main purpose is to reduce the possibility of ESD/EOS transient energy coupling to nearby or underlying sensitive high-speed signal traces or power paths before passing through the TVS protection components. Secondly, the shorter the distance between the transient energy entering the connector and the TVS protection component being released to the ground, the smaller the electromagnetic interference caused by the circuit. In addition, if the transient energy passes through components such as Common Mode Choke, capacitors or resistors before contacting TVS protection components, electromagnetic waves will be emitted to interfere with system operation, causing system malfunction or crash.
● L2 - Refers to the distance between the TVS protection component and the I/O of the Chipset. Under the premise that the total length from the connector to the Chipset IC remains unchanged, the shorter L1 is, the longer L2 will be. This will help increase the inductance value on the discharge path, thereby reducing the shunt current flowing to L2 and reducing the transient voltage amplitude flowing to the Chipset IC. There are even products that directly use wire winding to extend the length of L2 during design as a method to assist in achieving ESD/EOS design goals.
● As shown in Figure 1, L3- refers to the T-shaped branch layout routing added to the original I/O trace in order to connect the TVS protection components. When the ESD/EOS transient surge current flows through L3 and causes the parasitic inductance, it will directly increase the overall clamping voltage, which will have a huge impact on the design of the protection circuit. Therefore, when designing, L3 should be made as small as possible so that the TVS protective components will not have poor protection effects due to the effects of L3.
● Additional attention should be paid to the fact that if the TVS is grounded, it also needs to be directly connected to a large-area GND layer. If a GND trace design is used, additional inductance will be caused, which will also directly increase the overall clamping voltage performance, seriously affecting the design effectiveness of the protection circuit.
2. Precautions for PCB Layout of TVS protective components (uses the USB2.0 as an example)
Figure 2. Layout example of 6-pin TVS protective component on dual USB2.0
● It is recommended that the VDD pin of the TVS protection component be directly connected to the USB Port VBUS power trace, and try to avoid the inductance effect caused by the above-mentioned T-shaped branch trace or VIA when passing through the layer.
● The GND pin of the TVS protective component should be directly connected to the large-area GND layer in the PCB Layout. Avoid using PCB Trace to connect the GND pin of the protective component.
● As shown in Figure 2, when performing PCB Layout of multi-channel TVS protection components, the VDD or GND pin may need to be connected using VIA. It is recommended to use two or more VIA through holes for PCB penetration during design. The purpose is to reduce the ground impedance value and reduce the inductance effect.
● As shown in Figure 2, the 6-pin TVS is placed as close to the Connector as possible, and the routing should be shortened as much as possible. Avoid the possibility of the aforementioned coupling to adjacent or lower-layer signals or power paths, and also minimize the electromagnetic wave interference generated when discharging ESD/EOS energy.
● When designing signal line protection, the PAD of the TVS protection component should be designed directly on the signal line trace as much as possible to avoid the additional inductance caused by the T-shaped branch path from affecting the effectiveness of the protection component. The following actual layout case can be referred for comparison.
Case 1: Wrong PCB Layout method
Figure 3. Wrong protection component layout method
As shown in Figure 3, the PCB layout of the signal line is connected to the protection component through a T-shaped branch path (shown in the blue box in Figure 3), which will cause the protection circuit clamping voltage to rise and increase the risk of ESD/EOS energy shunting to internal circuits, which may ultimately cause the protection components to fail their intended effect.
Case 2: Correct PCB Layout method
Figure 4. Correct layout of protective components
As shown in Figure 4, the PCB layout of the signal line is designed with the protective component PAD directly on the signal routing. It conforms to the layout guideline of the signal line in Figure 2 and does not cause additional T-shaped branch paths (as shown in the blue box in Figure 4), which ensures that when ESD/EOS energy enters the Connector, the protective components can provide the best protection effect.
Conclusion:
With the trend of miniaturization of electronic products, it is necessary to pay attention to the placement and layout of protective components on the PCB to avoid incorrect routing that will lead to poor ESD/EOS protection effects. Therefore, when designing a protection circuit, after selecting correct and effective TVS protection components, properly completing the PCB Layout is also an important factor that affects the final protection result.